Title:
半導体ウェハ及び半導体ウェハの製造方法
Document Type and Number:
Japanese Patent JP4773413
Kind Code:
B2
Abstract:
A susceptor for a semiconductor wafer to be placed on during deposition of a layer on a front surface of the semiconductor wafer by chemical vapor deposition (CVD), has a gas-permeable structure with a porosity of at least 15% and a density of from 0.5 to 1.5 g/cm3. There is also a semiconductor wafer having a back surface and a front surface which has been coated by chemical vapor deposition (CVD) and a polished or etched back surface. The nanotopography of the back surface, expressed as the height fluctuation PV (=peak to valley), is less than 5 nm. There is a process for producing the semiconductor wafer.
Inventors:
Reinhard Schauer
Norbert Werner
Norbert Werner
Application Number:
JP2007260183A
Publication Date:
September 14, 2011
Filing Date:
October 03, 2007
Export Citation:
Assignee:
Siltronic AG
International Classes:
C23C16/458; C23C16/44; H01L21/205; C30B25/12; C30B25/18; C30B29/36; H01L21/02; H01L21/20; H01L21/44; H01L21/68; H01L21/683; H01L21/687
Domestic Patent References:
| JP2003229370A | ||||
| JP4324625A | ||||
| JP4149081A | ||||
| JP2003532612A | ||||
| JP63040763A |
Foreign References:
| WO2001086035A1 |
Attorney, Agent or Firm:
Toshio Yano
Takuya Kuno
Einzel Felix-Reinhard
Takuya Kuno
Einzel Felix-Reinhard