Title:
相補的バイポーラ技術を用いたサンプルおよび保持装置
Document Type and Number:
Japanese Patent JP4794025
Kind Code:
B2
Abstract:
The sampler-holder circuit (10) comprises an input follower stage (12) with input receiving a voltage (Vin) and outputs (SV1, SV2), the switching stages (14,16) with control inputs (H1,H2,H3,H4), for switching between a follower and a separation states, and outputs (SC1, SC2), the first follower transistors (T13,T14) with emitters connected to one terminal of the sampling capacitor (CE), the second transistors (T15,T17) with emitters connected to the current sources (S7,S8) and the bases connected to a potential redoubling that of the sampling capacitor, and the third transistors (T19,T20), digitally controlled to conduct when the switching stage is separating, and to block when the switching stage is following, with the emitters connected to the bases of the first transistors and the bases to the emitters of the second transistors. The circuit also comprises an additional sampling capacitor (CA) and the fourth transistors (T16,T18) with the bases connected to the outputs (SC1,SC2) of the switching stages (14,16), and the emitters connected to one terminal of the additional capacitor for the application of a voltage redoubling that on the basic capacitor (CE). The additional capacitor (CA) has a lower value than the basic capacitor (CE). The first (T13,T14) and the third (T19,T20) transistors are with the first type conductivity channels, e.g. n-p-n, and the second transistors (T15,T17) are of complementary type, e.g. p-n-p. The input follower (12) effects the redoubling of the input voltage (Vin) with an offset. The first output (SV1) is with a positive voltage offset, and the second output (SV2) is with a negative voltage offset, with respect to the input. The outputs (SV1,SV2) of the input follower stage are connected to the sampling capacitor (CE) via a two-route sampling circuit of symmetrical structure, the two component sampling circuits being identical but with transistors of complementary type. The output reading amplifier stage (18), with input (EA) and output (S), comprises an input Darlington stage and an output stage, each comprising three transistors including one of complementary type.
Inventors:
Laurent Simony
Application Number:
JP2000074983A
Publication Date:
October 12, 2011
Filing Date:
March 16, 2000
Export Citation:
Assignee:
E2V Semiconductors
International Classes:
G11C27/02; H03K17/00
Domestic Patent References:
| JP991988A | ||||
| JP63131400A | ||||
| JP7176199A |
Attorney, Agent or Firm:
Sonoda Yoshitaka
Kobayashi Yoshinori
Kobayashi Yoshinori