Title:
グラフィックスエンジンマスターモード動作の改良
Document Type and Number:
Japanese Patent JP4798849
Kind Code:
B2
Abstract:
An apparatus that allows for high capacity and fast access command queuing without requiring excess host processor overhead clock gating apparatus that is cost efficient and allows power conservation is provided. A command and its associated data to be processed by a graphics engine are formatted as data structures and first stored in system memory. A number of these data structures can be queued in system memory at any given time. Each data structure includes a header that provides information related to the data words in the data structure such as the number of the data words involved, their destination address, and others. Using the header information provided, the command and its associated data are sequentially provided to the graphics engine for processing.
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Inventors:
Nokara, Narasimha
Benkatapuram, Prarad
Benkatapuram, Prarad
Application Number:
JP2000614115A
Publication Date:
October 19, 2011
Filing Date:
April 24, 2000
Export Citation:
Assignee:
Nvidia Corporation
International Classes:
G06F9/38; G06F15/16; G06F15/167; G06F15/177; G06T11/00
Domestic Patent References:
| JPH02278475A | 1990-11-14 | |||
| JPH03142775A | 1991-06-18 | |||
| JPH09305789A | 1997-11-28 | |||
| JPH09251288A | 1997-09-22 | |||
| JPH0877366A | 1996-03-22 |
Foreign References:
| EP0780761B1 | 2001-08-08 | |||
| US6091863A | 2000-07-18 |
Attorney, Agent or Firm:
Yuichi Yamada
Masakazu Noda
Ikeda adult
Hidesaku Yamamoto
Masakazu Noda
Ikeda adult
Hidesaku Yamamoto