Title:
非常にコンパクトな不揮発性メモリおよびその方法
Document Type and Number:
Japanese Patent JP4814521
Kind Code:
B2
Abstract:
A non-volatile memory device capable of reading and writing a large number of memory cells with multiple read/write circuits in parallel has an architecture that reduces redundancy in the multiple read/write circuits to a minimum. The multiple read/write circuits are organized into a bank of similar stacks of components. In one aspect, each stack of components has individual components factorizing out their common subcomponents that do not require parallel usage and sharing them as a common component serially. Other aspects, include serial bus communication between the different components, compact I/O enabled data latches associated with the multiple read/write circuits, and an architecture that allows reading and programming of a contiguous row of memory cells or a segment thereof. The various aspects combined to achieve high performance, high accuracy and high compactness.
Inventors:
Sernia, Raoul-Adrian
Application Number:
JP2004539870A
Publication Date:
November 16, 2011
Filing Date:
September 18, 2003
Export Citation:
Assignee:
SanDisk Corporation
International Classes:
G11C16/06; G11C7/06; G11C7/10; G11C7/18; G11C16/02; G11C16/04; G11C16/10; G11C16/26
Domestic Patent References:
| JPH1055688A | 1998-02-24 | |||
| JPH09297996A | 1997-11-18 | |||
| JPH1173790A | 1999-03-16 | |||
| JPH1027473A | 1998-01-27 |
Foreign References:
| US5940329A | 1999-08-17 |
Attorney, Agent or Firm:
Toshi Inoguchi