Title:
表示駆動回路
Document Type and Number:
Japanese Patent JP4871533
Kind Code:
B2
Abstract:
Display data D1 to Dn are latched by a data latch, and are supplied to AND gates which are gate-controlled by a blanking signal/BLK. Output signals from the AND gates are delayed by delay circuits having different time delays of τ1 to τn, and then supplied to drivers. Subsequently, the output signals are supplied to a display device as driving signals Q1 to Qn. The timings of changes of signals S1 to Sn supplied to the drivers are distributed by the delay circuits, so that the timings of currents i1 to in flowing through the drivers are also distributed. Accordingly, a sum Σi of the currents i1 to in changes gradually over time, thereby decreasing the peak current.
Inventors:
Takahiro Imayoshi
Ishimasa Tsuneu
Ishimasa Tsuneu
Application Number:
JP2005176512A
Publication Date:
February 08, 2012
Filing Date:
June 16, 2005
Export Citation:
Assignee:
LAPIS Semiconductor Co., Ltd.
International Classes:
H03K17/00; G02F1/133; G09G3/20; H03K17/16
Domestic Patent References:
| JP5110266A | ||||
| JP2003008424A | ||||
| JP8022267A | ||||
| JP5346770A | ||||
| JP61255395A | ||||
| JP8321773A | ||||
| JP2002158568A | ||||
| JP2000286697A |
Attorney, Agent or Firm:
Kakimoto Yasunari