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Title:
リードフレームとそれを用いた半導体装置及びその生産方法
Document Type and Number:
Japanese Patent JP4901776
Kind Code:
B2
Abstract:

To provide a semiconductor device in which an interface void, package warpage, deformation of an electrode shape in polishing the backside etc. hardly occur when a resin sealed package is formed on a lead frame 1 made of whole copper alloy, and to provide a method of manufacturing the same.

A lead frame 1, in which a pattern such as a die pad and a lead that are required to be left in the package is connected by a thin jointing bar 13, is used. When the resin sealing package is formed by using this, a void near a die surface on the lower side is removed in polishing the backside, and the package warpage can be reduced because a sealing resin 11 reaches the die surface on the lower side and is cured. In addition, the shape deformation of an electrode 16 in polishing the backside is remarkably improved by a clogging prevention effect of a polishing stone because a metal occupied area of a polishing surface is reduced.

COPYRIGHT: (C)2008,JPO&INPIT


Inventors:
Yukiyuki Nose
Application Number:
JP2008024408A
Publication Date:
March 21, 2012
Filing Date:
February 04, 2008
Export Citation:
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Assignee:
Panasonic Corporation
International Classes:
H01L23/50
Domestic Patent References:
JP2000091488A
JP2000058735A
JP9321210A
JP2001015671A
JP10050921A
JP8017988A
JP6252330A
JP6244351A
Attorney, Agent or Firm:
Takuji Yamada
Mitsuo Tanaka
Mikio Takeuchi