Title:
ゼロレイテンシ機能、ゼロバスターンアラウンド機能を有するシンクロナスフラッシュメモリ
Document Type and Number:
Japanese Patent JP4902325
Kind Code:
B2
Abstract:
A synchronous flash memory includes an array of non-volatile memory cells. The memory array is arranged in rows and columns, and can be further arranged in addressable blocks. Data communication connections are used for bi-directional data communication with an external device, such as a processor or other memory controller. A data buffer can be coupled to the data communication connections to manage the bi-directional data communication. This buffer can be a pipelined input/output buffer circuit. Finally, a write latch is coupled between the data buffer and the memory array to latch data provided on the data communication connections. One method of operating a synchronous memory device comprises receiving write data on data connections, latching the write data in a write latch, and releasing the data connections after the write data is latched. A read operation can be performed on the synchronous memory device while the write data is transferred from the write latch to memory cells. Further, the memory device does not require any clock latency during a write operation.
Inventors:
Looper bar, Frankie, F.
Application Number:
JP2006315272A
Publication Date:
March 21, 2012
Filing Date:
November 22, 2006
Export Citation:
Assignee:
Round Rock Research, LRC
International Classes:
G11C16/02; G06F13/16; G06F13/42; G11C7/10; G11C8/18; G11C16/06; G11C16/10; G11C16/26
Domestic Patent References:
| JP6180999A | ||||
| JP2000076877A | ||||
| JP11073771A | ||||
| JP2000057769A | ||||
| JP11353874A |
Foreign References:
| WO1998039773A1 | ||||
| US5696917 |
Attorney, Agent or Firm:
Takehiro Chiba