Title:
メモリ装置の構造
Document Type and Number:
Japanese Patent JP4903481
Kind Code:
B2
Abstract:
In an improved construction of a memory device, the memory device includes a first group of pins via which a command/address signals are received and via which data signals are received, and a second group of pins via which the command/address signals are received and via which data signals are output. When the data signals are input to the first group of pins, the command/address signals are received via the second group of pins. When the data signals are output from the second group of pins, the command/address signals are received via the first group of pins.
Inventors:
Cui Jun
Application Number:
JP2006118310A
Publication Date:
March 28, 2012
Filing Date:
April 21, 2006
Export Citation:
Assignee:
Samsung Electronics Co.,Ltd.
International Classes:
G11C11/401
Domestic Patent References:
| JP6076581A | ||||
| JP2001135084A | ||||
| JP11328971A | ||||
| JP7326185A | ||||
| JP6096583A | ||||
| JP54134934A | ||||
| JP8321171A |
Attorney, Agent or Firm:
Masatake Shiga
Takashi Watanabe
Yasuhiko Murayama
Shinya Mitsuhiro
Takashi Watanabe
Yasuhiko Murayama
Shinya Mitsuhiro