Title:
ディジタル遅延線中のタップ位置の管理
Document Type and Number:
Japanese Patent JP4904596
Kind Code:
B2
Abstract:
This method of reading a plurality of chip sample values at tap positions (66, 68) in a digital delay line (64) having a starting point and an end point for delaying symbols of a signal (82) received in a receiver comprises:—reading the plurality of chip sample values in the digital delay line (64) at the tap positions (66, 68) according to a chip rate clock (70) having a chip rate clock cycle and a chip rate clock frequency,—oversampling the received signal (82) according to a sample rate clock (84) having a sample rate clock cycle and a sample rate clock frequency to produce a plurality of chip sample values supplied in the digital delay line (64), the sample rate clock frequency being higher than the chip rate clock frequency,—shifting the tap positions (66, 68) towards either the starting point or the end point of the digital delay line (64), and—adjusting the chip rate clock cycle when shifting the tap positions.
Inventors:
Mark, Wallis
Application Number:
JP2007543965A
Publication Date:
March 28, 2012
Filing Date:
November 30, 2005
Export Citation:
Assignee:
Estee-Ericsson, Society, Anonymous
International Classes:
H04B1/709; H04B1/707
Domestic Patent References:
| JP2000174661A | ||||
| JP2002290273A |
Foreign References:
| WO2004047327A1 |
Attorney, Agent or Firm:
Hirohito Katsunuma