Title:
貼り合わせウエーハの製造方法
Document Type and Number:
Japanese Patent JP4918229
Kind Code:
B2
Abstract:
The present invention provides a method for manufacturing a bonded wafer, which includes at least the steps of bonding a bond wafer and a base wafer, grinding an outer peripheral portion of the bonded bond wafer, etching off an unbonded portion of the ground bond wafer, and then reducing a thickness of the bond wafer, wherein, in the step of grinding the outer peripheral portion, the bonded bond wafer is ground so as to form a groove along the outer peripheral portion of the bond wafer to form an outer edge portion outside the groove; and in the subsequent step of etching, the outer edge portion is removed together with the groove portion of the bond wafer to form a terrace portion where the base wafer is exposed at the outer peripheral portion of the bonded wafer. Thus, it is possible to provide a method for manufacturing a bonded wafer, which can reduce the number of dimples formed in a terrace portion of a base wafer upon removing an outer peripheral portion of a bonded bond wafer.
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Inventors:
Shin Miyazaki
Tokio Takei
Keiichi Okabe
Tokio Takei
Keiichi Okabe
Application Number:
JP2005160439A
Publication Date:
April 18, 2012
Filing Date:
May 31, 2005
Export Citation:
Assignee:
Shin-Etsu Semiconductor Co., Ltd.
Nagano Electronics Co., Ltd.
Nagano Electronics Co., Ltd.
International Classes:
H01L21/02; H01L21/304; H01L21/306; H01L21/762; H01L27/12
Domestic Patent References:
| JP2005123263A | ||||
| JP7099295A | ||||
| JP10083986A | ||||
| JP58155157A | ||||
| JP2000091175A |
Foreign References:
| WO2005027728A1 |
Attorney, Agent or Firm:
Mikio Yoshimiya