Title:
自己整合ウェハまたはチップ構造、自己整合積層構造およびそれを製造する方法
Document Type and Number:
Japanese Patent JP4922193
Kind Code:
B2
Abstract:
A self-aligned wafer or chip structure including a substrate, at least one first concave base, at least one second concave base, at least one connecting structure and at least one bump is provided. The substrate has a first surface and a second surface, and at least one pad is formed on the first surface. The first concave base is disposed on the first surface and electrically connected to the pad. The second concave base is disposed on the second surface. The connecting structure passes through the substrate and disposed between the first and second concave bases so as to be electrically connected to the first and second concave bases. The bump is filled in the second concave base and protrudes out of the second surface.
Inventors:
Chen Eitai
What Satoshi
Shu Shuun
What Satoshi
Shu Shuun
Application Number:
JP2008007871A
Publication Date:
April 25, 2012
Filing Date:
January 17, 2008
Export Citation:
Assignee:
INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
International Classes:
H01L25/065; H01L21/3205; H01L23/12; H01L23/52; H01L25/07; H01L25/18
Domestic Patent References:
| JP2003318178A | ||||
| JP4328857A | ||||
| JP2004200547A | ||||
| JP2000252413A | ||||
| JP10214919A | ||||
| JP2004296812A | ||||
| JP2000195987A | ||||
| JP9246319A | ||||
| JP2004134645A | ||||
| JP2007059652A |
Foreign References:
| WO2000055898A1 |
Attorney, Agent or Firm:
Kenji Sugimura
Kosaku Sugimura
Kiyoshi Kuruma
Shiro Fujitani
Tatsuya Sawada
Kosaku Sugimura
Kiyoshi Kuruma
Shiro Fujitani
Tatsuya Sawada