Title:
多重メモリアクセスレイテンシ時間をサポートするコンピュータメモリシステムにおける性能を改善するためのシステムおよび方法
Document Type and Number:
Japanese Patent JP4926963
Kind Code:
B2
Abstract:
A memory system having multiple memory devices reduces average access latency by enabling different latencies for different regions of physical memory, providing an address map conducive to placing frequently accessed memory addresses into the lowest latency regions of physical memory; and assigning the frequently accessed memory addresses to the lowest latency regions of physical memory.
Inventors:
Woo, Stephen, Sea.
Tsang, Brian H.
Tsang, Brian H.
Application Number:
JP2007527567A
Publication Date:
May 09, 2012
Filing Date:
May 20, 2005
Export Citation:
Assignee:
Rambus Incorporated
International Classes:
G06F12/06; G06F12/00; G06F13/16; G11C7/00
Domestic Patent References:
| JPH11242629A | 1999-09-07 | |||
| JPH11110280A | 1999-04-23 | |||
| JP2002342153A | 2002-11-29 | |||
| JP2003203481A | 2003-07-18 | |||
| JP2001290697A | 2001-10-19 | |||
| JPH06266615A | 1994-09-22 |
Foreign References:
| WO2004025478A1 | 2004-03-25 | |||
| US20020144071A1 | 2002-10-03 | |||
| US20020038405A1 | 2002-03-28 | |||
| US20020084458A1 | 2002-07-04 |
Attorney, Agent or Firm:
Yoshiyuki Inaba
Shinji Oga
Toshifumi Onuki
Shinji Oga
Toshifumi Onuki