Title:
半導体装置およびその製造方法
Document Type and Number:
Japanese Patent JP4956919
Kind Code:
B2
Abstract:
In a semiconductor device, capacitance between copper interconnections is decreased and the insulation breakdown is improved simultaneously, and a countermeasure is taken for misalignment via by a manufacturing method including the steps of forming an interconnection containing copper as a main ingredient in an insulative film above a substrate, forming insulative films and a barrier insulative film for a reservoir pattern, forming an insulative film capable of suppressing or preventing copper from diffusing on the upper surface and on the lateral surface of the interconnection and above the insulative film and the insulative film, forming insulative films of low dielectric constant, in which the insulative film is formed such that the deposition rate above the opposing lateral surfaces of the interconnections is larger than the deposition rate therebelow to form an air gap between the adjacent interconnections and, finally, planarizing the insulative film by interlayer CMP.
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Inventors:
Junji Noguchi
Takashi Matsumoto
Takafumi Oshima
Toshihiko Onozuka
Takashi Matsumoto
Takafumi Oshima
Toshihiko Onozuka
Application Number:
JP2005167676A
Publication Date:
June 20, 2012
Filing Date:
June 08, 2005
Export Citation:
Assignee:
株式会社日立製作所
International Classes:
H01L23/532; H01L21/768
Domestic Patent References:
| JP2005136152A | ||||
| JP2004193431A | ||||
| JP2003297918A | ||||
| JP2006120988A | ||||
| JP9237834A |
Foreign References:
| US6048802 | ||||
| US6303464 |
Attorney, Agent or Firm:
Manabu Inoue