To provide a semiconductor testing apparatus whose timing of application of a test pattern waveform common to each DUT by a test waveform application circuit is not different from those of individual test pattern waveforms, and whose circuit scale has been reduced.
The semiconductor testing apparatus which performs parallel tests while applying test pattern waveforms to a plurality of devices under measurement 12, is equipped with a pattern generator 101 for generating first test pattern data common to each device 12, a storage portion 103 for generating second test pattern data individual to each device 12, and a first selection circuit 105 for choosing either the first test pattern data or the second test pattern data.
COPYRIGHT: (C)2009,JPO&INPIT
Nobuya Kurebayashi
Jun Miyake
Akira Hotta
Rikitake Junpei
Daigo Suzuki
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