Title:
半導体装置の設計方法
Document Type and Number:
Japanese Patent JP5010322
Kind Code:
B2
Abstract:
A semiconductor device designing method includes calculating capacitance. The semiconductor device has a semiconductor substrate, an insulator formed on the semiconductor substrate, and an electrode formed on the insulator. The capacitance is calculated under an approximation assuming a portion of the semiconductor substrate, the insulator and a portion of the electrode to be one of a conductor and a dielectric depending on electric characteristics thereof, respectively.
Inventors:
Takayuki Shigeyuki
Kinoshita Shigeru
Hiroshi Watanabe
Toshitake Yaegashi
Kinoshita Shigeru
Hiroshi Watanabe
Toshitake Yaegashi
Application Number:
JP2007084989A
Publication Date:
August 29, 2012
Filing Date:
March 28, 2007
Export Citation:
Assignee:
Toshiba Corporation
International Classes:
H01L29/792; H01L21/336; H01L21/8247; H01L27/115; H01L29/788
Domestic Patent References:
| JP2001028405A |
Attorney, Agent or Firm:
Masahiko Hinataji