Title:
シミュレーション装置、シミュレーション方法、及び半導体装置の製造方法
Document Type and Number:
Japanese Patent JP5020562
Kind Code:
B2
Abstract:
Disclosed is a simulation apparatus including an input unit, storage unit, arithmetic unit, controller, and output unit. The input unit inputs a first potential at the source end, which corresponds to the gate end of a TFT, on that surface of a thin polysilicon film which faces the gate, a second potential at the source end on the back surface of the thin polysilicon film on which the gate is formed, a third potential at the drain end, which corresponds to the gate end of the TFT, on that surface of the thin polysilicon film which faces the gate, and a fourth potential at the drain end on the back surface of the thin polysilicon film. A drain current is calculated by performing an arithmetic operation on the basis of the first to fourth potentials, and a model is formed by including defect states.
Inventors:
Hiroshi Tsuji
Yoshiteru Shimizu
Yoshiteru Shimizu
Application Number:
JP2006202195A
Publication Date:
September 05, 2012
Filing Date:
July 25, 2006
Export Citation:
Assignee:
LCD Advanced Technology Development Center Co., Ltd.
International Classes:
H01L29/786; H01L21/336; H01L29/00
Domestic Patent References:
| JP2003110114A | ||||
| JP2003110113A | ||||
| JP2003110112A |
Attorney, Agent or Firm:
Makoto Nakamura
Kurata Masatoshi
Takashi Mine
Yoshihiro Fukuhara
Sadao Muramatsu
Kurata Masatoshi
Takashi Mine
Yoshihiro Fukuhara
Sadao Muramatsu