Title:
SRAM装置
Document Type and Number:
Japanese Patent JP5035335
Kind Code:
B2
Abstract:
An SRAM device uses a four-terminal double gate field effect transistor as a selection transistor, wherein the four-terminal double gate field effect transistor comprises a gate which drives the transistor and a gate which controls a threshold voltage, which are electrically separated from each other, on both surfaces of a standing semiconductor thin plate, and wherein a voltage used to reduce a threshold voltage is input to the gate which controls the threshold voltage of the selection transistor during a writing operation than during a reading operation. The SRAM device which can increase both the read and write margins is provided.
Inventors:
Shinichi Ouchi
Akira Uehara
Akira Uehara
Application Number:
JP2009505192A
Publication Date:
September 26, 2012
Filing Date:
March 14, 2008
Export Citation:
Assignee:
National Institute of Advanced Industrial Science and Technology
International Classes:
H01L27/11; G11C11/41; H01L21/8244
Domestic Patent References:
| JP2005260607A | 2005-09-22 | |||
| JP2005174960A | 2005-06-30 | |||
| JP2007201107A | 2007-08-09 | |||
| JP2007103629A | 2007-04-19 |
Attorney, Agent or Firm:
Sumio Tanai
Masatake Shiga
Masatake Shiga