Title:
デジタル信号のデューティ・サイクルを補正するための方法および装置
Document Type and Number:
Japanese Patent JP5041867
Kind Code:
B2
Abstract:
The disclosed methodology and apparatus measure and correct the duty cycle of a reference clock signal that a clock circuit supplies to a duty cycle measurement (DCM) circuit. In one embodiment, the DCM circuit includes a capacitor driven by a charge pump. The reference clock signal drives the charge pump. The clock circuit varies the duty cycle of the reference clock signal among a number of known duty cycle values. The DCM circuit stores resultant capacitor voltage values corresponding to each of the known duty cycle values in a data store. The DCM circuit applies a test clock signal having an unknown duty cycle to the capacitor via the charge pump, thus charging the capacitor to a new voltage value that corresponds to the duty cycle of the test clock signal. Control software accesses the data store to determine the duty cycle to which the test clock signal corresponds, thus providing a measured duty cycle. The apparatus generates an error signal when the measured duty cycle varies from a predetermined duty cycle. The apparatus includes a variable duty cycle clock generator that alters the duty cycle of the test clock signal to reduce the error.
Inventors:
Jimmy Qui
David William Bowstler
Escainder Heil
David William Bowstler
Escainder Heil
Application Number:
JP2007118363A
Publication Date:
October 03, 2012
Filing Date:
April 27, 2007
Export Citation:
Assignee:
INTERNATIONAL BUSINESS MASCHINES CORPORATION
International Classes:
H03L7/08; H03L7/093
Domestic Patent References:
| JP6249922A | ||||
| JP2005091206A | ||||
| JP11243327A | ||||
| JP2001194425A | ||||
| JP57044122B1 | ||||
| JP1253673A |
Attorney, Agent or Firm:
Takeshi Ueno
Tasaichi Tanae
Yoshihiro City
Hiroshi Sakaguchi
Tasaichi Tanae
Yoshihiro City
Hiroshi Sakaguchi