Title:
不揮発性半導体メモリ装置
Document Type and Number:
Japanese Patent JP5095083
Kind Code:
B2
Abstract:
A nonvolatile memory device includes a bit line, a pair of data lines and a plurality of scalable two transistor memory (STTM) cells. The memory cells are arranged between a pair of datalines so as to share the bit line. The memory device further includes a data line selection circuit and a sense amplification circuit. The data line selection circuit selects one of a pair of data lines, and the sense amplification circuit senses and amplifies a voltage difference between the bit line and the selected data line. Operation speed is increased, while improving device cell array structure.
Inventors:
Zhao Yue
Chokichi
Chokichi
Application Number:
JP2005000851A
Publication Date:
December 12, 2012
Filing Date:
January 05, 2005
Export Citation:
Assignee:
Mosside Technologies, Inc.
International Classes:
G11C16/04; G11C11/34; G11C11/404; G11C16/02; H01L27/115
Domestic Patent References:
| JP11111929A | ||||
| JP2002216482A | ||||
| JP2003217280A |
Foreign References:
| US5896327 | ||||
| US6882561 |
Attorney, Agent or Firm:
Yasuhiko Murayama
Masatake Shiga
Takashi Watanabe
Keiji Kiuchi
Masatake Shiga
Takashi Watanabe
Keiji Kiuchi