Title:
半導体パッケージ、電子部品、及び電子機器
Document Type and Number:
Japanese Patent JP5104315
Kind Code:
B2
Abstract:
Even when a substrate on which a semiconductor package has been mounted is made curved, stress upon electrical connections is mitigated, thereby eliminating faulty connections and improving connection reliability. A semiconductor chip (10) has electrodes (11) on a second face (10b) thereof. Support blocks (20), capable of bending and flexing, are placed at two locations on a peripheral edge of a first face (10a) of the semiconductor chip (10). An interposer (30) is placed so as to span the support blocks with the support blocks interposed between itself and the semiconductor chip (10), and has a wiring pattern in a flexible resin film. Two end portions of the interposer are folded back onto the side of the second face (10b) of the semiconductor chip (10), and the wiring pattern thereof is electrically connected to the electrodes (11) of the semiconductor chip (10).
Inventors:
Nobuhiro Mikami
Shinji Watanabe
Junya Sato
Atsushi Sawada
Shinji Watanabe
Junya Sato
Atsushi Sawada
Application Number:
JP2007545225A
Publication Date:
December 19, 2012
Filing Date:
November 13, 2006
Export Citation:
Assignee:
NEC
International Classes:
H01L23/12
Domestic Patent References:
| JP2002110839A | 2002-04-12 | |||
| JPH10125705A | 1998-05-15 | |||
| JPH10223826A | 1998-08-21 |
Attorney, Agent or Firm:
Kato Asamichi