To reduce the power consumption of a display device, using a time gradation system, when multiple gradation display is not necessary.
Differently from a 1st display mode of multiple gradations, a memory controller of a signal control circuit which the display device has eliminates writing of a digital video signal of the low rank bits to a memory in a 2nd display mode of two gradations. Further, reading of a digital video signal of the low rank bits from the memory is eliminated. The amount of information of a digital video signal inputted to a source signal line driving circuit is decreased. In response to the operation, a display controller lowers frequencies of a start pulse and clock pulses inputted to the source signal line driving circuit to lower a driving voltage. A frame period can be made longer than that of the 1st display mode by decreasing gradations to reduce the power consumption.
COPYRIGHT: (C)2004,JPO
Hajime Kimura
Yu Yamazaki
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