NICAM処理方法 - Freescale Semiconductor, Inc.

Title:

NICAM処理方法

Document Type and Number:

Japanese Patent JP5140594

Kind Code:

B2

Abstract:

A NICAM processor (82) comprises a first memory (100) for temporarily storing a current frame of A-channel and B-channel input data, wherein the current frame data is stored into the first memory at a first clock rate. A second memory (106, 108) temporarily stores companded A-channel and B-channel data of a previous frame in a format other than an interleaved format according to NICAM standard requirements. An interleaving circuit (105) reads the previous frame companded data from the second memory at a second clock rate and in a manner for interleaving the previous frame data into the NICAM standard required interleaved format. A bit stream generator (114) generates a first portion of an output bit stream, multiplexes it with a payload portion, and outputs the output bit stream, wherein the first portion comprises a frame alignment word, control information and additional data, and the payload portion comprises the interleaved data of the previous frame. A companding and storing circuit (104) compands the input data of the current frame and stores the companded data into the second memory at a third clock rate and in the format other than the NICAM interleaved format. The companding and storing circuit is operative during an interval within the current frame, subsequent to the storing into the first memory and the reading from the second memory.

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Inventors:

Zoso, Luciano
Chin, Alanpy
Lester, David Pee

Application Number:

JP2008533558A

Publication Date:

February 06, 2013

Filing Date:

September 25, 2006

Export Citation:

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