Title:
表示装置、およびそれを用いた電子機器
Document Type and Number:
Japanese Patent JP5177957
Kind Code:
B2
Abstract:
To provide a display which is made smaller in parasitic resistance and parasitic capacity and is hardly increased in delay time even if a delta array is used and a plurality of elements, such as static memories, are arranged within a pixel, and electronic equipment using the same.
In the delta array, pixel electrodes are arrayed by forming their shapes to a polygonal shape in the case of a large number of the elements, such as the static elements, or in the case of the large area of the elements required to be included in the pixel.
COPYRIGHT: (C)2007,JPO&INPIT
Inventors:
Jun Koyama
Hiroyuki Miyake
Shunpei Yamazaki
Hiroyuki Miyake
Shunpei Yamazaki
Application Number:
JP2006080563A
Publication Date:
April 10, 2013
Filing Date:
March 23, 2006
Export Citation:
Assignee:
Semiconductor Energy Laboratory Co., Ltd.
International Classes:
G09F9/30; G02F1/1368; G09G3/20; G09G3/36; H01L51/50; H05B33/12; H05B33/26
Domestic Patent References:
| JP4285917A | ||||
| JP2004163601A | ||||
| JP2003107505A | ||||
| JP2003108031A | ||||
| JP2003302946A | ||||
| JP2001222256A | ||||
| JP2002140036A | ||||
| JP2002221917A |
Foreign References:
| WO2004073356A1 |