Title:
メモリ制御装置
Document Type and Number:
Japanese Patent JP5205956
Kind Code:
B2
Abstract:
A memory control device that can improve the speed of a memory interface. A packet disassembly section disassembles packet data into segments and detects packet quality information. A memory management section has an address management table and manages a state in which the packet data is stored according to the packet quality information. A segment/request information disassembler disassembles the segments into data by an access unit by which memories can be written/read, and generates write requests and read requests according to the access unit. A memory access controller avoids a bank access to which is prohibited because of a bank constraint, extracts a write request or a read request corresponding to an accessible bank from the write requests or the read requests generated, and gains write/read access to the memories.
Inventors:
Hideki Sugai
Hiroshi Tomonaga
Satoshi Nemoto
Hiroshi Tomonaga
Satoshi Nemoto
Application Number:
JP2007335671A
Publication Date:
June 05, 2013
Filing Date:
December 27, 2007
Export Citation:
Assignee:
富士通株式会社
International Classes:
G06F12/06
Domestic Patent References:
| JP2003256275A | ||||
| JP2002344502A |
Attorney, Agent or Firm:
Takeshi Hattori