Title:
走査信号線駆動回路およびそれを備えた表示装置
Document Type and Number:
Japanese Patent JP5208277
Kind Code:
B2
Abstract:
A gate driver is provided with an odd-numbered stage shift register, an even-numbered stage shift register, and main lines including clock signal main lines. Each stage (bistable circuit) of one of the shift registers receives the first clock CKA and the second clock CKB from the clock signal main lines, and the third clock CKC and the fourth clock CKD from an adjacently provided stage of the other register (the odd-numbered stage shift register, if the stage is the even-numbered stage). Each stage of the shift register can receive the second clock CKB from a different stage of the same shift register. With this, it is possible to reduce a picture-frame area of a panel in a display device provided with a scanning signal line drive circuit having the plurality of shift registers.
Inventors:
Mayuko Sakamoto
Yasuaki Iwase
Yasuaki Iwase
Application Number:
JP2011522747A
Publication Date:
June 12, 2013
Filing Date:
February 17, 2010
Export Citation:
Assignee:
Sharp Corporation
International Classes:
G09G3/36; G02F1/133; G09G3/20
Domestic Patent References:
| JP2004287448A | 2004-10-14 | |||
| JP2009134814A | 2009-06-18 | |||
| JP2008146079A | 2008-06-26 | |||
| JP2007114761A | 2007-05-10 | |||
| JP2007316642A | 2007-12-06 | |||
| JP2006039524A | 2006-02-09 | |||
| JP2004287448A | 2004-10-14 | |||
| JP2009134814A | 2009-06-18 | |||
| JP2008146079A | 2008-06-26 |
Attorney, Agent or Firm:
Akihiro Shimada
Kenji Kawahara
Kenji Kawahara