Title:
不揮発性メモリ内蔵シフトレジスタ
Document Type and Number:
Japanese Patent JP5228195
Kind Code:
B2
Abstract:
To provide an element for a nonvolatile memory which enables manufacturing of an electrically rewritable nonvolatile memory in a process of manufacturing a standard CMOSIC, and offers superior availability for general purpose use, such as use for an integrated circuit adjustment.
The element for the nonvolatile memory includes PMOS transistors Tr1, Tr2, and NMOS transistor Tr3 each having a floating gate FG. The PMOS transistor Tr1 and the PMOS transistor Tr2 are formed on different wells separated from each other.
COPYRIGHT: (C)2009,JPO&INPIT
Inventors:
Masaaki Kamiya
Application Number:
JP2007111939A
Publication Date:
July 03, 2013
Filing Date:
April 20, 2007
Export Citation:
Assignee:
Interchip Corporation
International Classes:
H01L21/336; G11C16/04; H01L21/8247; H01L27/10; H01L27/115; H01L29/788; H01L29/792
Domestic Patent References:
| JP2005353984A | ||||
| JP10335505A | ||||
| JP2006080247A | ||||
| JP2002158301A | ||||
| JP8007582A | ||||
| JP48074131A |
Attorney, Agent or Firm:
Hiroyuki Kurihara
Muranaka
Muranaka