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Title:
SDRAMリフレッシュ回路
Document Type and Number:
Japanese Patent JP5254902
Kind Code:
B2
Abstract:

To provide a SDRAM refreshing memory capable of performing verification by setting a refreshing period equal to that of actual use.

The SDRAM refreshing circuit includes: a command monitoring part 11 for monitoring a refreshing command issued from a logical emulator 1 to a SDRAM 3; a replenishment refreshing command-issuing part 12 for issuing a replenishment refreshing command when the command monitoring part 11 detects the refreshing command; and a command selection part 13 for selecting the replenishment refreshing command when the replenishment refreshing command-issuing part 12 is allowed to issue the replenishment replenishing command, and for selecting the command from the logical emulator 1 when the replenishment refreshing command issuing part 12 is inhibited from issuing the replenishment refreshing command.

COPYRIGHT: (C)2011,JPO&INPIT


Inventors:
Kunio Sunada
Application Number:
JP2009182729A
Publication Date:
August 07, 2013
Filing Date:
August 05, 2009
Export Citation:
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Assignee:
Hitachi Information & Communication Engineering Co., Ltd.
International Classes:
G11C11/401; G11C11/406; G11C11/407
Domestic Patent References:
JP2006031124A
JP2002245794A
JP2000132420A
Other References:
中村祐一、外1名,FPGAとPCの連携によるSystem On a Chipの検証手法,情報処理学会研究報告,日本,社団法人情報処理学会,2003年 1月29日,Vol.2003、No.7,pp.25~30(SLDM108-5)
Attorney, Agent or Firm:
Kiyoshi Tanaka
Murayama Midori