Title:
半導体集積回路及びその制御方法、並びに情報処理装置
Document Type and Number:
Japanese Patent JP5292925
Kind Code:
B2
Abstract:
A semiconductor integrated circuit includes a circuit block (210) connected to an arithmetic processing unit (190) via a bus (50), a power supply noise data generator (220,231) which is configured to generate a power supply noise data signal by converting power supply noise generated in power supply voltage of power supply operates the circuit block, an error detector (260) which is configured to detect an error of data outputted from the circuit block to the bus, and a write controller (250) which is configured to associate power supply noise information based on the power supply noise data signal with data on the bus and write the data in a storage unit (280), and to stop to write the data in response to the detection of the error by the error detector.
Inventors:
Takashi Yamamoto
Koji Ishizuka
Ueki Toshikazu
Owaki Takeshi
Atsushi Morosawa
Koji Ishizuka
Ueki Toshikazu
Owaki Takeshi
Atsushi Morosawa
Application Number:
JP2008142072A
Publication Date:
September 18, 2013
Filing Date:
May 30, 2008
Export Citation:
Assignee:
富士通株式会社
International Classes:
G06F12/16
Domestic Patent References:
| JP2004212387A | ||||
| JP2005527062A | ||||
| JP6324985A | ||||
| JP5298193A | ||||
| JP2007219846A |
Attorney, Agent or Firm:
Junichi Yokoyama