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Title:
ビット列間のエラー制御コードをエンコードする方法およびエンコードシステム
Document Type and Number:
Japanese Patent JP5336501
Kind Code:
B2
Abstract:
An encoding system for encoding error control codes may include a first encoder configured to encode an input bit stream to generate first bit streams of C-bits, where c is an integer greater than zero, and a second encoder may be configured to receive the first bit streams and shuffle data of the received first bit streams to generate second bit streams. The data shuffling of the first bit streams may adjust an error distribution of the second bit streams. An encoding method may include encoding an input bit stream to generate first bit streams of C-bits, and receiving the first bit streams and shuffling data of the received first bit streams to generate second bit streams. An error distribution of the second bit streams may be adjusted based on the data shuffling.

Inventors:
Heath Yoon
Jae Hong Kim
Sun Chun Park
Application Number:
JP2010531953A
Publication Date:
November 06, 2013
Filing Date:
May 19, 2008
Export Citation:
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Assignee:
Samsung Electronics Company Limited
International Classes:
H03M13/27
Domestic Patent References:
JP7143098A
JP2007049723A
JP2003304176A
JP6112928A
JP8097731A
JP3847993B2
Foreign References:
WO2006136883A1
Other References:
Boris Polianskikh et al.,Design and implementation of error detection and correction circuitry for multilevel memory protection,Multiple-Valued Logic, 2002. ISMVL 2002. Proceedings 32nd IEEE International Symposium on,2002年
Masashi Takata et al.,Multiple Programming Method and Circuitry for a Phase Change Nonvolatile Random Access Memory(PRAM),IEICE Transactions on Electronics,2004年10月 1日,Vol.E87-C, No.10,pp.1679-1685
Attorney, Agent or Firm:
Masatake Shiga
Takashi Watanabe
Shinya Mitsuhiro