Title:
パラレル連想メモリ
Document Type and Number:
Japanese Patent JP5339544
Kind Code:
B2
Abstract:
[Object] To provide a parallel CAM that can perform the parity check fast at the search time. [Solution] The CAM 10 for searching all the addresses at the same time and determining whether or not the same data as input data is stored comprises a write search parity generator 12 for generating parities WP and SP of n-bit write and search data WD and SD, respectively, a plurality of memory locations 14 corresponding to a plurality of addresses, and a NAND circuit 16 for activating a parity error signal PE if at least one of valid parity match signals PMV outputted from the memory locations 14 is inactive. Each memory location 14 comprises n data memory cells 2, a parity memory cell 3, an exclusive OR circuit 20 for judging whether or not the parity SP and a parity RP are matched, and activating a parity match signal /PM, if they are matched, and a NAND circuit 22 for validating the parity match signal /PM using a data match signal DML.
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Inventors:
Miyatake Hisada
Application Number:
JP2010535711A
Publication Date:
November 13, 2013
Filing Date:
August 04, 2009
Export Citation:
Assignee:
INTERNATIONAL BUSINESS MACHINES CORPORATION
International Classes:
G11C15/04
Domestic Patent References:
| JPH1027481A | 1998-01-27 | |||
| JP2002279785A | 2002-09-27 | |||
| JPS63177242A | 1988-07-21 | |||
| JP2004247006A | 2004-09-02 | |||
| JPH0922595A | 1997-01-21 | |||
| JPH1027481A | 1998-01-27 | |||
| JP2002279785A | 2002-09-27 | |||
| JPS63177242A | 1988-07-21 | |||
| JP2004247006A | 2004-09-02 |
Attorney, Agent or Firm:
Takeshi Ueno
Tasaichi Tanae
Yoshihiro City
Tasaichi Tanae
Yoshihiro City