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Title:
低抵抗のチップ形抵抗器とその製造方法
Document Type and Number:
Japanese Patent JP5373912
Kind Code:
B2
Abstract:
Provided are a low-resistance chip resistor having a simple structure in which self-independence is given and the mechanical strength is increased for durability, and an easier and faster method of manufacturing same.  A low-resistance chip resistor characterized in that resistive layers are formed on both the front and back surfaces of an insulating substrate, or insulating substrates are formed on both the front and back surfaces of a resistive layer, that in the former, protective films are formed on the central portions of the resistive layers in the longitudinal direction and surface and back electrodes are formed on the resistive layers on both sides of the protective films, and in the latter, surface and back electrodes are formed on the resistive layers on both sides of the substrates, and that in both the former and latter, end surface electrodes are provided at both ends in the width direction.

Inventors:
Osamu Matsukawa
Hirano Tatsuki
Atsushi Toda
Application Number:
JP2011526658A
Publication Date:
December 18, 2013
Filing Date:
August 11, 2009
Export Citation:
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Assignee:
Kamaya Electric Co., Ltd.
International Classes:
H01C3/00
Domestic Patent References:
JPH0621593A1994-01-28
JPH09320802A1997-12-12
JP2004022710A2004-01-22
JP2006313763A2006-11-16
JPS59182592A1984-10-17
JPH0621593A1994-01-28
JPH09320802A1997-12-12
JP2004022710A2004-01-22
Foreign References:
WO2009028215A12009-03-05
Attorney, Agent or Firm:
Hajime Sakai
Masahiro Kurai