Title:
半導体装置及びその製造方法
Document Type and Number:
Japanese Patent JP5378707
Kind Code:
B2
Abstract:
To provide a semiconductor device with improved reliability. The semiconductor device includes a wiring board, a microcomputer chip flip-chip bonded over the wiring board via gold bumps, a first memory chip laminated over the microcomputer chip, wires for coupling the first memory chip to the wiring board, an underfill material with which a flip-chip coupling portion of the microcomputer chip is filled, and a sealing member for sealing the microcomputer chip and the first memory chip with resin. Further, the corner of a second opening portion of a solder resist film of the wiring board corresponding to the corner of the chip on the air vent side in charging the underfill material is made close to the microcomputer chip, which can improve the wettability and spread of the underfill material at the second opening portion, thus reducing the exposure of leads to the second opening portion, thereby improving the reliability of the semiconductor device.
Inventors:
Yusuke Ota
Sugiyama Michiaki
Ishikawa Tomokazu
Okada Mikako
Sugiyama Michiaki
Ishikawa Tomokazu
Okada Mikako
Application Number:
JP2008141285A
Publication Date:
December 25, 2013
Filing Date:
May 29, 2008
Export Citation:
Assignee:
Renesas Electronics Corporation
International Classes:
H01L23/28; H01L21/56; H01L23/12
Domestic Patent References:
| JP2009277915A | ||||
| JP2005150179A | ||||
| JP11214586A | ||||
| JP2008252027A | ||||
| JP2009147007A | ||||
| JP2005175113A | ||||
| JP2001127198A | ||||
| JP200185826A | ||||
| JP11145328A | ||||
| JP200649477A | ||||
| JP5327195A | ||||
| JP10190203A |
Attorney, Agent or Firm:
Yamato Tsutsui