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Title:
応力補償組成物、応力補償組成物によって導電性バンプを形成する方法、及び半導体部品
Document Type and Number:
Japanese Patent JP5415657
Kind Code:
B2
Abstract:
A semiconductor component (10) having a photodefinable stress compensation layer (21) and composition for the stress compensation material. The photodefinable stress compensation material is formed on a semiconductor wafer (11) and openings (22) are made photolithographically. Conductive bumps (26) are then disposed thereon and additional conductive bumps (28) are formed on the original conductive bumps (26). The photodefinable stress compensation material is composed of a photoinitiator, an epoxy having a first index of refraction, a diluent, and a filler. The indices of refraction of the epoxy-diluent combination and the filler are approximately equal. Alternatively, the photodefinable stress compensation material can be formed on a semiconductor wafer (11) having conductive bumps (46) disposed thereon. Openings (49) are formed in the stress compensation layer (47) to expose the conductive bumps (46). Additional conductive bumps (51) are formed on the original conductive bumps (46).

Inventors:
Lizabeth Ann Caser
Trellian fan
Application Number:
JP2000201009A
Publication Date:
February 12, 2014
Filing Date:
July 03, 2000
Export Citation:
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Assignee:
Freescale Semiconductor, Inc.
International Classes:
C08K3/34; H01L21/60; C08L5/00; C08L63/00; C08L101/00; H01L21/312; H01L21/768; H01L23/12; H01L23/28; H01L23/29; H01L23/31
Domestic Patent References:
JP11145142A
JP9194573A
JP10251615A
JP2143584A
JP311756A
JP969539A
Attorney, Agent or Firm:
Atsushi Honda



 
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