Title:
電気光学装置及び電子機器並びにトランジスター
Document Type and Number:
Japanese Patent JP5488136
Kind Code:
B2
Abstract:
A semiconductor layer of a TFT is continuously formed from an inside of an open hole portion overlapping with an intersection up to an outside of the open hole portion and includes a first source/drain area electrically connected to a surface portion of the data line exposed to a bottom surface of the open hole portion, a channel area disposed on a side wall of the open hole portion, and a second source/drain area formed outside the open hole portion and electrically connected to the pixel electrode. The gate electrode of the TFT is formed inside the open hole portion so as to overlap with at least the channel area and is electrically connected to a scanning line.
Inventors:
Tatsuya Ishii
Application Number:
JP2010086765A
Publication Date:
May 14, 2014
Filing Date:
April 05, 2010
Export Citation:
Assignee:
Seiko Epson Corporation
International Classes:
G09F9/30; G02F1/1368; H01L29/786
Domestic Patent References:
| JP2009081383A | ||||
| JP2008151900A | ||||
| JP2008072093A | ||||
| JP2003282881A | ||||
| JP2007072114A |
Attorney, Agent or Firm:
Masahiko Ueyanagi
Osamu Suzawa
Kazuhiko Miyasaka
Osamu Suzawa
Kazuhiko Miyasaka