Title:
シミュレーション装置及びシミュレーション方法
Document Type and Number:
Japanese Patent JP5504960
Kind Code:
B2
Abstract:
To easily verify a design target.
A detection part 11 detects an address range on a memory 22 in which each function executed in a design target 20 is arranged or an address on the memory 22 in which an instruction that moves between functions is arranged. A functional stack generation part 12 compares the address of each instruction executed in the design target 20 with the address range on the memory 22 in which each function is arranged or the address of the instruction that moves between the functions, and generates a functional stack indicative of call relations between the functions according to the result of the comparison.
COPYRIGHT: (C)2011,JPO&INPIT
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Inventors:
Takayuki Sasaki
Junichi Niizuma
Hiroaki Fujimoto
Takashi Fujita
Yoshikazu Motomura
Junichi Niizuma
Hiroaki Fujimoto
Takashi Fujita
Yoshikazu Motomura
Application Number:
JP2010035920A
Publication Date:
May 28, 2014
Filing Date:
February 22, 2010
Export Citation:
Assignee:
富士通株式会社
International Classes:
G06F11/28
Domestic Patent References:
| JP5134903A | ||||
| JP5216715A | ||||
| JP2000276373A | ||||
| JP1229328A |
Attorney, Agent or Firm:
Takeshi Hattori