Title:
設計検証プログラム、設計検証方法および設計検証装置
Document Type and Number:
Japanese Patent JP5540887
Kind Code:
B2
Abstract:
In a design verification apparatus, a priority resolver selects one or more verification datasets for verifying a procedure described in a design specification of a target product, in response to a verification request for that procedure. The priority resolver determines a priority score of each parameter that the selected verification datasets specify as a constraint on the procedure. A verification order resolver determines a verification order of the selected verification datasets, based on the priority scores determined by the priority resolver. An output processor produces data identifying the verification datasets, together with indication of the determined verification order.
Inventors:
Ryosuke Oishi
Plavin Kumar Multi
Rafael Kazumichi Morizawa
Plavin Kumar Multi
Rafael Kazumichi Morizawa
Application Number:
JP2010119167A
Publication Date:
July 02, 2014
Filing Date:
May 25, 2010
Export Citation:
Assignee:
富士通株式会社
International Classes:
G06F17/50; G06F11/22
Domestic Patent References:
| JP10040316A |
Attorney, Agent or Firm:
Takeshi Hattori