Title:
半導体装置
Document Type and Number:
Japanese Patent JP5543629
Kind Code:
B2
Abstract:
PROBLEM TO BE SOLVED: To enhance the degree-of-freedom of wiring for connecting a memory chip and a controller chip, in a semiconductor device including a package structure where the memory chip and controller chip are laminated on a wiring board.SOLUTION: A memory card 1A includes a wiring board 2 and four memory chips M1-M4 laminated on the principal surface thereof, and a controller chip 3 and an interposer 4 mounted on the surface of the memory chip M4 of the uppermost layer. The memory chips M1-M4 are laminated, respectively, on the surface of the wiring board 2 while directing the long side in the same direction as that of the long side of the wiring board 2. The memory chip M1 of the lowermost layer is mounted on the wiring board 2 while being shifted by a predetermined distance in the tip direction of the memory card 1A so that it does not overlap the pad 9 of the wiring board 2. Three memory chips M2-M4 laminated on the memory chip M1 are arranged so that the short side on the side where a pad 6 is formed is located at the tip of the memory card 1A.
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Inventors:
Minoru Shinohara
Michiaki Sugiyama
Makoto Araki
Michiaki Sugiyama
Makoto Araki
Application Number:
JP2013029646A
Publication Date:
July 09, 2014
Filing Date:
February 19, 2013
Export Citation:
Assignee:
ルネサス electronics incorporated company
International Classes:
H01L25/065; H01L25/07; H01L25/18
Attorney, Agent or Firm:
Tsutsui Daiwa