Title:
集積回路構造
Document Type and Number:
Japanese Patent JP5574365
Kind Code:
B2
Abstract:
An integrated circuit structure includes an active power supply line and a data-retention power supply line. A memory macro is connected to the active power supply line and the data-retention power supply line. The memory macro includes a memory cell array and a switch. The switch is configured to switch a connection between connecting the memory cell array to the active power supply line and connecting the memory cell array to the data-retention power supply line. The data-retention power supply line is outside of the memory macro.
Inventors:
李 政 宏
廖 宏 仁
廖 宏 仁
Application Number:
JP2010086356A
Publication Date:
August 20, 2014
Filing Date:
April 02, 2010
Export Citation:
Assignee:
Taiwan Semiconductor Manufacturing 股ふん, Inc. Taiwan Semiconductor Manufacturing Company, Ltd.
International Classes:
H01L21/8242; G11C11/413; H01L21/822; H01L27/04; H01L27/10; H01L27/108
Attorney, Agent or Firm:
Hisao Fukami
Toshio Morita
Gihei Nakamura
Yutaka Horii
Nobuo Arakawa
Masato Sasaki
Toshio Morita
Gihei Nakamura
Yutaka Horii
Nobuo Arakawa
Masato Sasaki