Title:
半導体記憶装置
Document Type and Number:
Japanese Patent JP5599977
Kind Code:
B2
Abstract:
To provide a plurality of memory banks, each of which is divided into a plurality of segments; a bank address register that designates a memory bank that becomes a refresh target; a segment address register that designates a segment that becomes a refresh target; and a refresh control circuit that prohibits a refresh operation of the memory bank or the segment not designated by at least one of the bank address register and the segment address register. This semiconductor device is capable of designating whether to perform a refresh operation not only in a memory bank unit but also in a segment unit within the memory bank, and thus it achieves a further reduction of the power consumption.
Inventors:
Toshiyuki Ichimura
Application Number:
JP2009012077A
Publication Date:
October 01, 2014
Filing Date:
January 22, 2009
Export Citation:
Assignee:
P. S. Fau ルクスコ SARL PS4 Luxco S. a. r. l.
International Classes:
G11C11/406
Attorney, Agent or Firm:
Mitsuhiro Washizu
Ogata Japanese
Yasuyuki Kurose
Takuya Mitani
Ogata Japanese
Yasuyuki Kurose
Takuya Mitani