Title:
電荷層を軽減した集積回路構造およびこれを形成する方法
Document Type and Number:
Japanese Patent JP5610557
Kind Code:
B2
Abstract:
A method, integrated circuit and design structure includes a silicon substrate layer having trench structures and an ion impurity implant. An insulator layer is positioned on and contacts the silicon substrate layer. The insulator layer fills the trench structures. A circuitry layer is positioned on and contacts the buried insulator layer. The circuitry layer comprises groups of active circuits separated by passive structures. The trench structures are positioned between the groups of active circuits when the integrated circuit structure is viewed from the top view. Thus, the trench structures are below the passive structures and are not below the groups of circuits when the integrated circuit structure is viewed from the top view.
Inventors:
ベチュラ、アラン、ビー
ジョセフ、アルヴィン、ジェイ
スリンクマン、ジェイムズ、エー
ウォルフ、ランディー、エル
ジョセフ、アルヴィン、ジェイ
スリンクマン、ジェイムズ、エー
ウォルフ、ランディー、エル
Application Number:
JP2013523205A
Publication Date:
October 22, 2014
Filing Date:
July 28, 2011
Export Citation:
Assignee:
インターナショナル・ビジネス・マシーンズ・コーポレーションＩＮＴＥＲＮＡＴＩＯＮＡＬ ＢＵＳＩＮＥＳＳ ＭＡＣＨＩＮＥＳ ＣＯＲＰＯＲＡＴＩＯＮ
International Classes:
H01L27/04; H01L21/336; H01L21/762; H01L21/822; H01L27/12; H01L29/786
Attorney, Agent or Firm:
Tsuyoshi Ueno
Tasa Kind 1
Tasa Kind 1