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Title:
薄膜トランジスタ製造装置
Document Type and Number:
Japanese Patent JP5629154
Kind Code:
B2
Abstract:
In an apparatus for fabricating a thin film transistor, amorphous silicon is deposited on a substrate in a first multi-chamber and is crystallized into polycrystalline silicon without using a separate process chamber or multi-chamber, and the substrate deposited with the amorphous silicon is loaded into a second multi-chamber for forming electrodes, thereby making it possible to minimize a characteristic deviation and improve fabrication process efficiency. The apparatus includes a first multi-chamber in which amorphous silicon is deposited on a substrate, a second multi-chamber in which electrodes are formed on the substrate, and a loading/unloading chamber interposed between the first multi-chamber and the second multi-chamber. The loading/unloading chamber includes a substrate holder on a lower side thereof and a power voltage supplier on an upper side thereof.

Inventors:
金 秉胄
安 志洙
劉 ▲チョル▼浩
金 聖哲
Application Number:
JP2010171837A
Publication Date:
November 19, 2014
Filing Date:
July 30, 2010
Export Citation:
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Assignee:
三星ディスプレイ株式會社Samsung Display Co.,Ltd.
International Classes:
H01L21/02; H01L21/20; H01L21/336; H01L29/786
Attorney, Agent or Firm:
Eye Py Dee international patent business corporation