Title:
信頼性のあるマイクロコントローラ並びにその設計方法及びそのためのコンピュータプログラム
Document Type and Number:
Japanese Patent JP5631848
Kind Code:
B2
Abstract:
A microcontroller comprising a central processing unit (50, 51) and a further fault processing unit (11) suitable for performing validation of operations of said central processing unit (50, 51). The further fault processing unit (11) is external and different with respect to said central processing unit (51) and said further fault processing unit (11) comprises at least a module for performing validation of operations of said central processing unit and one or more modules suitable for performing validation of operations of other functional parts of said microcontroller (10). Validation of operations of said central processing unit (51) is performed by using one or more of the following fault tolerance techniques: data shadowing; code&flow signature; data processing legality check; addressing legality check; ALU concurrent integrity checking; concurrent mode/interrupt check. The proposed microcontroller is particularly suitable for application in System On Chip (SoC) and was developed by paying specific attention to the possible use in automotive System On Chip. The invention also includes a method for designing and verify such fault-robust system on chip, and a fault-injection technique based on e-language.
Inventors:
リッカルド・マリアーニ
シルヴァーノ・モット
モニア・チャヴァッチ
シルヴァーノ・モット
モニア・チャヴァッチ
Application Number:
JP2011248216A
Publication Date:
November 26, 2014
Filing Date:
November 14, 2011
Export Citation:
Assignee:
ヨジテック・ソシエタ・ペル・アチオニＹＯＧＩＴＥＣＨ Ｓｐａ
International Classes:
G06F11/18; G06F11/00; G06F11/30; G06F11/22; G06F11/267; G06F11/27; G06F15/78
Attorney, Agent or Firm:
Yamada Takuji
Mitsuo Tanaka
Mitsuo Tanaka