Title:
パスゲートを備えた半導体記憶装置
Document Type and Number:
Japanese Patent JP5701831
Kind Code:
B2
Abstract:
According to an embodiment, a semiconductor storage device includes an SRAM cell. The SRAM cell includes first and second transfer gates each comprising a pass gate. The pass gate includes first and second tunnel transistors. The first tunnel transistor includes a first conductivity type first diffusion region as a source or drain region, a second conductivity type second diffusion region as a drain or source region, and a gate electrode supplied with a control voltage. The second tunnel transistor includes a first conductivity type first diffusion region as a source or drain region, a second conductivity type second diffusion region as a drain or source region electrically connected to the second diffusion region of the first tunnel transistor, and a gate electrode electrically connected to the gate electrode of the first tunnel transistor.
Inventors:
Keisuke Nakatsuka
Shigeru Kawanaka
Shigeru Kawanaka
Application Number:
JP2012196366A
Publication Date:
April 15, 2015
Filing Date:
September 06, 2012
Export Citation:
Assignee:
Toshiba Corporation
International Classes:
H01L21/8244; H01L27/11
Domestic Patent References:
| JP2012084797A | ||||
| JP2011166142A | ||||
| JP9162394A | ||||
| JP2003008021A | ||||
| JP2005004934A | ||||
| JP2007234793A |
Foreign References:
| US20080068895 |
Attorney, Agent or Firm:
Hirohito Katsunuma
Yasukazu Sato
Yasushi Kawasaki
Takeshi Sekine
Akaoka Akira
Katsumi Ozawa
Yasukazu Sato
Yasushi Kawasaki
Takeshi Sekine
Akaoka Akira
Katsumi Ozawa