Title:
半導体装置
Document Type and Number:
Japanese Patent JP5725679
Kind Code:
B2
Abstract:
PROBLEM TO BE SOLVED: To provide a static type memory cell which is highly integrated by using a SGT and secures operation stability.SOLUTION: A semiconductor storage device according to the present invention is composed of static type memory cells in which six MOS transistors are arranged on a substrate. Each of the six MOS transistors comprises: first and second NMOS access transistors for accessing a memory; third and fourth NMOS driver transistors for driving a storage node for storing data of the memory cells; and first and second PMOS load transistors for supplying an electric charge for storing the data of the memory cells. In the first and second NMOS access transistors for accessing the memory, a first diffusion layer, a columnar semiconductor layer and a second diffusion layer are arranged hierarchically in a direction perpendicular to the substrate, the columnar semiconductor layer is arranged between the first diffusion layer and the second diffusion layer, and a gate is formed on a side wall of the columnar semiconductor layer.
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Inventors:
Fujio Masuoka
Hiroki Nakamura
Hiroki Nakamura
Application Number:
JP2013230377A
Publication Date:
May 27, 2015
Filing Date:
November 06, 2013
Export Citation:
Assignee:
Unisantis Electronics Singapore Pte Ltd.
International Classes:
H01L21/8244; H01L21/8234; H01L21/8238; H01L27/08; H01L27/088; H01L27/092; H01L27/11; H01L29/786
Domestic Patent References:
| JP2010123721A | ||||
| JP8148582A | ||||
| JP2002237529A |
Foreign References:
| WO2009154293A1 | ||||
| WO2009095998A1 |
Attorney, Agent or Firm:
Koichi Tsujii
Sadao Kumakura
Fumiaki Otsuka
Takaki Nishijima
Hiroyuki Suda
Hiroshi Uesugi
Sadao Kumakura
Fumiaki Otsuka
Takaki Nishijima
Hiroyuki Suda
Hiroshi Uesugi