Title:
再構築ウエハの生産中にチップを位置付けするための方法
Document Type and Number:
Japanese Patent JP5732696
Kind Code:
B2
Abstract:
A method for fabricating a re-built wafer which comprises chips having connection pads, comprising: fabricating a first wafer of chips, production on this wafer of a stack of at least one layer of redistribution of the pads of the chips on conductive tracks designed for the interconnection of the chips, this stack being designated the main RDL layer, cutting this wafer in order to obtain individual chips each furnished with their RDL layer, transferring the individual chips with their RDL layer to a sufficiently rigid support to remain flat during the following steps, which support is furnished with an adhesive layer, with the RDL layer on the adhesive layer, depositing a resin in order to encapsulate the chips, polymerizing the resin, removing the rigid support, depositing a single redistribution layer called a mini RDL in order to connect the conductive tracks of the main RDL layer up to interconnection contacts, through apertures made in the adhesive layer, the wafer comprising the polymerized resin, the chips with their RDL layer and the mini RDL being the re-built wafer.
Inventors:
Val, Christian
Application Number:
JP2012514490A
Publication Date:
June 10, 2015
Filing Date:
June 14, 2010
Export Citation:
Assignee:
3D PLUS
International Classes:
H01L23/12
Domestic Patent References:
| JP2009043857A | ||||
| JP2005167191A | ||||
| JP2006173234A | ||||
| JP6013181U |
Attorney, Agent or Firm:
Takahisa Kimura