Title:
ストリング選択線及びビット線の改善されたコンタクトレイアウトを有する３次元メモリアレイ
Document Type and Number:
Japanese Patent JP5759285
Kind Code:
B2
Abstract:
A 3D memory device includes a plurality of ridges, in some embodiments ridge-shaped, in the form of multiple strips of conductive material separated by insulating material, arranged as bit lines which can be coupled through decoding circuits to sense amplifiers. The strips of conductive material have side surfaces on the sides of the stacks. A plurality of conductive lines arranged as word lines which can be coupled to row decoders, extends orthogonally over the plurality of stacks. The conductive lines conform to the surface of the stacks. Memory elements lie in a multi-layer array of interface regions at cross-points between side surfaces of the semiconductor material strips on the stacks and the conductive lines. The memory elements are programmable, like the anti-fuses or charge trapping structures. In some embodiments, the 3D memory is made using only two critical masks for multiple layers. Some embodiments include a staircase-shaped structure positioned at ends of the semiconductor material strips. Some embodiments include SSL interconnects on a metal layer parallel to the semiconductor material strips, and further SSL interconnects on a higher metal layer, parallel to the word lines.
Inventors:
Toshio Hong
Lu Hakoba
Akira Shin
Lu Hakoba
Akira Shin
Application Number:
JP2011140819A
Publication Date:
August 05, 2015
Filing Date:
June 24, 2011
Export Citation:
Assignee:
Muang Hong Electronic Co., Ltd.
International Classes:
H01L21/8247; G11C16/04; G11C17/06; G11C17/14; H01L21/336; H01L27/10; H01L27/105; H01L27/115; H01L29/786; H01L29/788; H01L29/792; H01L45/00; H01L49/00
Domestic Patent References:
| JP2008078404A | ||||
| JP2009111345A | ||||
| JP2008258458A | ||||
| JP2008192708A |
Foreign References:
| US20080031048 | ||||
| US20090310425 |
Attorney, Agent or Firm:
Sakuo Yamaguchi