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Title:
半導体装置
Document Type and Number:
Japanese Patent JP5782330
Kind Code:
B2
Abstract:
A semiconductor device includes a plurality of memory arrays and a plurality of memory array control circuits. Each of the plurality of memory array control circuits includes a read/write control circuit for controlling a read/write operation for the memory array, and a selection circuit for selecting and activating the memory array based on a clock signal and an output signal from the read/write control circuit.

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Inventors:
Hisashi Iwamoto
Yano Yuji
Issei Inoue
Application Number:
JP2011174011A
Publication Date:
September 24, 2015
Filing Date:
August 09, 2011
Export Citation:
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Assignee:
Renesas Electronics Corporation
International Classes:
G06F12/00; G06F12/06; G11C7/00
Domestic Patent References:
JP2005196343A
JP2007200213A
JP200336205A
JP2008152687A
JP2013109813A
JP201481672A
JP201474993A
Attorney, Agent or Firm:
Fukami patent office



 
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