Title:
複数の低電力モードを有するデータプロセッサ
Document Type and Number:
Japanese Patent JP5791207
Kind Code:
B2
Abstract:
A processor includes a first virtual terminal, a second virtual terminal, circuitry coupled to the first virtual terminal for providing current to the first virtual terminal, a first regulating transistor coupled between the first virtual terminal and the second virtual terminal, a first disabling transistor coupled in parallel with the first regulating transistor for selectively disabling the first regulating transistor by directly connecting the second virtual terminal to the first virtual terminal, a second regulating transistor coupled between the second virtual terminal and a first power supply voltage terminal, and a second disabling transistor coupled in parallel with the second regulating transistor for selectively disabling the second regulating transistor by directly connecting the second virtual terminal to the first power supply voltage terminal.
Inventors:
Ramaraju, Ravindra Large
Bearden, David Earl.
Cooper, Troy El.
Bearden, David Earl.
Cooper, Troy El.
Application Number:
JP2013512625A
Publication Date:
October 07, 2015
Filing Date:
April 20, 2011
Export Citation:
Assignee:
Freescale Semiconductor, Inc.
International Classes:
G06F1/32; G06F15/78
Domestic Patent References:
| JP2009505588A | ||||
| JP2007150761A | ||||
| JP2007104572A | ||||
| JP2004096073A | ||||
| JP2001053599A | ||||
| JP5108194A |
Foreign References:
| WO2007099841A1 |
Attorney, Agent or Firm:
Atsushi Honda