Title:
半導体装置
Document Type and Number:
Japanese Patent JP5813678
Kind Code:
B2
Abstract:
According to one embodiment, a semiconductor device using multi-layered graphene wires includes a substrate having semiconductor elements formed therein, a first graphene wire formed above the substrate and including a multi-layered graphene layer having a preset impurity doped therein, a second graphene wire formed on the same layer as the first multi-layered graphene wire above the substrate and including a multi-layered graphene layer into which the preset impurity is not doped, a lower-layer contact connected to the undersurface side of the first multi-layered graphene wire, and an upper-layer contact connected to the upper surface side of the second multi-layered graphene wire.
Inventors:
Makoto Wada
Hisao Miyazaki
Akihiro Kajita
Atsunobu Isobayashi
Tatsuro Saito
Tadashi Sakai
Hisao Miyazaki
Akihiro Kajita
Atsunobu Isobayashi
Tatsuro Saito
Tadashi Sakai
Application Number:
JP2013027925A
Publication Date:
November 17, 2015
Filing Date:
February 15, 2013
Export Citation:
Assignee:
Toshiba Corporation
International Classes:
H01L27/10; H01L21/3205; H01L21/336; H01L21/768; H01L21/8247; H01L23/532; H01L27/115; H01L29/788; H01L29/792
Domestic Patent References:
| JP2012080014A | ||||
| JP2011023420A | ||||
| JP2006190998A | ||||
| JP2014141379A |
Attorney, Agent or Firm:
Suzue International Patent Office