Title:
プロシージャリターンシーケンスを加速するための方法およびシステム
Document Type and Number:
Japanese Patent JP5815596
Kind Code:
B2
Abstract:
A method for retrieving a return address from a link stack when returning from a procedure in a pipeline processor is disclosed. The method identifies a retrieve instruction operable to retrieve a return address from a software stack. The method further identifies a branch instruction operable to branch to the return address. The method retrieves the return address from the link stack, in response to both the instruction and the branch instruction being identified and fetches instructions using the return address.
Inventors:
Michael William Morrow
James Norris Defender Fur
James Norris Defender Fur
Application Number:
JP2013095916A
Publication Date:
November 17, 2015
Filing Date:
April 30, 2013
Export Citation:
Assignee:
QUALCOMM INCORPORATED
International Classes:
G06F9/42; G06F9/38
Domestic Patent References:
| JP2011503718A | ||||
| JP2001100993A | ||||
| JP7281892A | ||||
| JP7239782A | ||||
| JP2003256197A | ||||
| JP2010501963A |
Foreign References:
| US5812813 | ||||
| US6374350 |
Other References:
本永朝雄,6809アセンブリプログラミング,日本,株式会社サイエンス社,1986年11月25日,初版,Pages:62-68
Stephen B. Fubber,VLSI RISC Architecture and Organization,米国,Marcel Dekker Inc.,1989年,Pages:231-233
Stephen B. Fubber,VLSI RISC Architecture and Organization,米国,Marcel Dekker Inc.,1989年,Pages:231-233
Attorney, Agent or Firm:
Kurata Masatoshi
Yoshihiro Fukuhara
Morisezo Iseki
Okumura Motohiro
Yoshihiro Fukuhara
Morisezo Iseki
Okumura Motohiro